Technologies

O-SIP

Technologies

O-SIP?

LIPAC's O-SIP (Optical-System in Package) is a core component of an optical system by integrating an optical device (Photonic IC) and an electronic device (Electronic IC) into one semiconductor package. There are no restrictions on the types of devices that can be integrated through O-SIP, and they can have different materials (Si, SiGe, InGaAs, InP, Glass) and different functions (analog function, digital function, photonic function). Various devices can be integrated into one semiconductor packaging. Therefore, O-SIP is a versatile 'optical packaging platform' technology that can produce ultra-small, highly integrated optical systems.

“O-SIP: An optical system which can integrate optical devices and electronic devices into one semiconductor packaging”

The O-SIP manufacturing process is based on the advanced semiconductor packaging technology. It is leading the growth of the current semiconductor technology and industry by overcoming the limitation of Moore's law. A prime example of such a change is that the update of the ITRS, which has been the industry standard of Moore's Law, ended in 2015, and the HI Roadmap was newly enacted and became the standard for the semiconductor industry. Therefore, advanced semiconductor packaging technology will continue to advance as one of the main-streams of driving the semiconductor industry and technology in the future.

Among the semiconductor packaging methods, the most advanced technology is Fan Out Wafer Level Package (FOWLP). The conventional semiconductor packaging method uses a way of packaging individual chips one by one, such as the Chip On Board (COB) method or the Flip Chip method as shown in the figure below. This requires wiring and molding for each chip during packaging, so investment in mass production equipment must be made proportional to the increase in quantity.

This packaging method of individual chips has evolved into a method of packaging many chips at once in a wafer level as shown in the figure below. In this case, since wafer processing equipment is used, additional investment costs for production equipment are reduced whereas the quantity increases.

Among the Wafer Level Packaging methods, the WLCSP (Wafer Level Chip Scale Package) method, which packages the wafer without reconfiguration, allows the PAD to be located only within the chip area, so only Fan-In connection is possible as shown in the figure below. In order to overcome this limit to connect a larger number of PADs, fan out wiring is required as shown in the figure below.

In the FOWLP method, the wafer is reconfigured through die rearrangements, and the wiring process is performed using a semiconductor process to connect the fan out connection. In the process of wafer reconfiguration through die rearrangement, multiple dies can be rearranged so that they can be included in the wafer, making it possible to implement System In Package through multiple chips within the package.

O-SIP Structure

The O-SIP can include various structures and functions as shown below.

1. Vertical Optical Direction
Inside

Co-packaged IC

  • Photonic IC with vertical light direction (VCSEL, PD, APD, LED, etc.)
  • Electrical IC (Driver IC, TIA, Memory, Processor, Passive components, etc.)

Electrical Connection

  • ReDistribution Layer (RDL)
Outside

Optical Component

  • Micro-lens array
  • Guide Pattern

Electrical Connection

  • BGA (Ball Grid Array)
  • LGA (Land Grid Array)

It is an O-SIP structure suitable for optical devices in which light enters and exits perpendicular to the surface of the chip. This is the applicable packaging platform when using VCSEL (Vertical Cavity Surface Emitting Laser), PD (Photodiode), APD (Avalanche Photodiode), LED (Light Emitting Diode). There is no limit to the number of electronic devices that can be included, and various digital and analog devices made of Si, SiGe, GaAs, etc. can also be integrated. Each IC is electrically interconnected within the package by a Redistribution Layer (RDL). Standardized BGA (Ball Grid Array) or LGA (Land Grid Array) can be used for external connection terminals. MLA (Micro Lens Array) and Guide Patterns can be manufactured on the surface, which can be manufactured using a semiconductor process that uses photolithography as a wafer level, enabling precise and efficient manufacturing.

2 . Lateral Optical Direction
Inside

Co-packaged IC

  • Photonic IC with lateral light direction (DFB Laser, EML, SiPh PLC, Silica PLC, photodiode)
  • Electrical IC (Driver IC, TIA, Memory, Processor, thermistor, Passive components, etc.)

Electrical Connection

  • ReDistribution Layer (RDL)
Outside

Optical Component

  • Micro-lens array
  • Guide Pattern

Electrical Connection

  • BGA (Ball Grid Array)
  • LGA (Land Grid Array)

It is an O-SIP structure suitable for optical devices in which light enters and exits horizontally compared to the surface of the chip. Edge emitting laser diodes can be used in this case including DFB (Distributed Feedback) Laser, EML (Electroabsorption Modulated Laser), etc. In addition, monitoring PDs and electronic devices can be packaged together. The O-SIP with vertical and lateral optical direction can be implemented simultaneously within one package.

3. Vertical Optical Direction with stacked IC
Inside

Co-packaged IC

  • Photonic IC with lateral light direction (DFB Laser, EML, SiPh PLC, Silica PLC, photodiode)
  • Electrical IC (Driver IC, TIA, Memory, Processor, thermistor, Passive components, etc.)

Electrical Connection

  • ReDistribution Layer (RDL)
Outside

Optical Component

  • Micro-lens array
  • Guide Pattern

Optical IC

  • CMOS image sensor, TOF sensor, SPAD array, PD, CCD, etc.

Electrical IC

  • Passive components

Electrical Connection

  • BGA (Ball Grid Array)
  • LGA (Land Grid Array)

It is a structure that reduces the footprint of packaging by stacking ICs on the package in a two-layer structure. After PAD is formed on the surface of the FOWLP, the stacked chips can be packaged using either Wire Bonding, Flip Chip Bonding, or SMT (Surface Mount Technology) methods.

Advantages of O-SIP

  1. 1. Compact Size

    The FOWLP method is considered as the method that can realize the thinnest and smallest package among semiconductor packaging methods. Since FOWLP uses a substrate-less structure that does not include a separate board or PCB without any wire bonding, it is suitable for realizing a light, thin, and small package. Therefore, it is adequate for high-speed/large-bandwidth data transmission by integrating multiple packages or for mobile applications where the size limitation is critical.

  2. 2. Mass Production Availability

    In the FOWLP method, the process is carried out in a wafer level, and semiconductor production equipment is used. Therefore, unlike the COB method that conducts wire bonding individually, the production capacity can be easily increased to billions of units without additional equipment investment. Securing such production capacity is an important part of IoT and mobile applications.

  3. 3. Competitive Price

    Since the process is carried out in a wafer level, the unit price of the Optical Engine will drop sharply as the quantity increases.

  4. 4. Outperforming Performance

    Since packaging can be manufactured with high precision using semiconductor equipment and processes, it is suitable for optical applications requiring high alignment precision. In addition, since wire bonding is not used at all and a fine semiconductor wiring layer is used for electrical connection, excellent signal integrity can be obtained. Therefore, it is suitable for application to high-speed data transmission products such as optical interconnections.

Packaging Process

Optical System in Package

  • Chip placement

    Using ‘Pick and Place’ machine, components are re-arranged on the adhesive-attached carrier with PAD side down.

  • Wafer level molding

    Molding in a wafer level with Epoxy Mold Compound.

  • Release from carrier

    Releasing the molded EMC & chips by removing adhesives from carrier, which leads to get re-configured form of wafer.

  • Redisribution layer formation

    Forming a Cu re-distribution layer and insulators to connect components after turning over the molded EMC and chips.

  • Lens formation and ball open

    Forming the ball grid array for external electrical connections. If necessary, MEMS process is applied to have micro lens array or guide pattern.

  • Singulation

    Sawing the wafer in the form of chip package.

Terms of service

약관내용